The challenges presented in Section 2.1.1Opportunities are
not fundamental, but stem from inefficient communication patterns
dictated by inflexible software. All identified bottlenecks
are avoided when superfluous
communication is removed and the remainder is restructured to
reduce memory system stress, which equates to minimizing the number of
times data is touched and serving it from cache to avoid contention.
One way to accomplish this feat on diverse combinations of processors and
memory regions is to adapt application structure to hardware both
in terms of computation and communication.
Subsections
willem
2010-02-03